zXc developments

Quick example accomplishing an RS Latch with Verilog Data Flow.

module rs_latch( q, qn, s, r );
 
        input s, r;
        output q, qn;
 
        assign qn = ~( s & q );
        assign q  = ~( r & qn );
 
endmodule

This entry was posted on Saturday, December 12th, 2009 at 6:50 pm and is filed under Verilog. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.