Verilog RS Latch

Shawn — Sat, 12 Dec 2009 18:50:01 +0000

Quick example accomplishing an RS Latch with Verilog Data Flow.

module rs_latch( q, qn, s, r );
 
        input s, r;
        output q, qn;
 
        assign qn = ~( s & q );
        assign q  = ~( r & qn );
 
endmodule

Three Bit Multiplication

Shawn — Sun, 21 Jun 2009 15:20:42 +0000

Here is an example of a three bit multiplication in Verilog made to fit into a EPM7160SLC84-10.

I think I wrote a four bit one that I will try to find.

/*****************************
        Description of Multiplier:
                Three bit multiplication with
                macrocell count.
------------------------------
        Date:    2.28.2006
        Version: 1.0
*****************************/
module multiplier( valA, valB, result );
 
/*****************************
         Inputs:
*****************************/
        input [2:0] valA;
        input [2:0] valB;
 
/*****************************
        Outputs:
*****************************/
        output [7:0] A;
 
/*****************************
        Wires:
*****************************/
        wire [5:0] mp0, mp1, mp2;
 
        assign mp0 = (valB[0]) ? { 2'b00, valA }      : 5'b00000;
        assign mp1 = (valB[1]) ? { 1'b0, valA, 1'b0 } : 5'b00000;
        assign mp2 = (valB[2]) ? { valA, 2'b00 }      : 5'b00000;
 
        assign result = mp0 + mp1 + mp2;
 
endmodule

zXc developments » Verilog

Verilog RS Latch

Three Bit Multiplication